While laser “melt” anneal processes for transistor source and/or drain (i.e., source/drain) formation are known, they are not typical in high volume logic device manufacturing. One forecasted application for a pulsed laser anneal process is to melt semiconductor material in the source/drain. The melt advantageously increases the activation of dopants relative to other forms of anneal where the semiconductor is not melted, thereby improving transistor parametrics, such as external resistance (Rext), specific contact resistance (Rc), etc. The melt is possible in a planar architectures in part because for a crystalline semiconductor substrate, or perhaps an insulating field dielectric surrounds the sides of the source/drain, forming a “bowl” capable of containing the melt.
For non-planar architectures, for example where a semiconductor fin structure is formed, the source/drain is typically elevated from the surroundings such that a laser melt anneal can cause a raised source/drain to flow, losing its desired shape, structural relationship to, and/or electrical continuity with, the channel region of the transistor.
Non-planar architectures benefiting from the higher source/drain dopant activation possible through laser anneal and techniques for performing such laser anneals are therefore advantageous.